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4.5 FT245R FIFO Timing Diagrams
Figure 6 - FIFO Read Cycle
T6
T2
T5
T4
RXF#
RD#
T1
T3
Valid Data
Max
D[7...0]
Table 3 - FIFO Read Cycle Timings
Time
T1
Description
Min
Unit
ns
RD Active Pulse Width
50
T2
RD to RD Pre-Charge Time
RD Active to Valid Data*
Valid Data Hold Time from RD Inactive*
RD Inactive to RXF#
50 + T6
ns
T3
20
0
50
25
ns
T4
ns
T5
0
ns
T6
RXF Inactive After RD Cycle
80
ns
* Load = 30pF
Figure 7 - FIFO Write Cycle
T12
T8
T11
TXE#
WR
T7
T9
T10
Valid Data
D[7...0]
Table 4 - FIFO Write Cycle Timings
Time
T7
Description
Min
50
50
20
0
Max
Unit
ns
WR Active Pulse Width
T8
WR to RD Pre-Charge Time
Data Setup Time before WR Inactive
Data Hold Time from WR Inactive
WR Inactive to TXE#
ns
T9
ns
T10
T11
T12
ns
5
25
ns
TXE Inactive After WR Cycle
80
ns
FT245R USB UART I.C. Datasheet Version 1.05
© Future Technology Devices International Ltd. 2005
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
