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4.5 FT245R FIFO Timing Diagrams
Figure 6 - FIFO Read Cycle
T6
RXF#
T5
RD#
T3
T1
T2
T4
Valid Data
D[7...0]
Table 3 - FIFO Read Cycle Timings
Time
T1
T2
T3
T4
T5
T6
Description
RD Active Pulse Width
RD to RD Pre-Charge Time
RD Active to Valid Data*
Valid Data Hold Time from RD Inactive*
RD Inactive to RXF#
RXF Inactive After RD Cycle
Min
50
50 + T6
20
0
0
80
Max
Unit
ns
ns
50
25
ns
ns
ns
ns
* Load = 30pF
Figure 7 - FIFO Write Cycle
T11
T12
TXE#
T7
T8
WR
D[7...0]
Table 4 - FIFO Write Cycle Timings
Time
T7
T8
T9
T10
T11
T12
T9
Valid Data
T10
Description
WR Active Pulse Width
WR to RD Pre-Charge Time
Data Setup Time before WR Inactive
Data Hold Time from WR Inactive
WR Inactive to TXE#
TXE Inactive After WR Cycle
Min
50
50
20
0
5
80
Max
Unit
ns
ns
ns
ns
25
ns
ns
FT245R USB UART I.C. Datasheet Version 1.05
© Future Technology Devices International Ltd. 2005
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
