Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.3
Clearance No.: FTDI #199
4.10 CPU-style FIFO Interface Mode Description
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT232H. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0). When the FT232H is in CPU-style Interface mode, the IO signal lines are configured as given in
The following Truth-Table 4.7 gives the decode values for particular operations.
CS#
1
0
0
A0
X
0
1
RD#
X
Read Data Pipe
Read Status
WR
X
Write Data Pipe
Send Immediate
Table 4.6 CPU-Style FIFO Interface Operation Select
The Status read is shown in Table 4.7
Data Bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Data
1
1
1
1
X
X
X
X
Status
Data available (=RXF)
Space available (=TXE)
Suspend
Configured
X
X
X
X
Table 4.7 CPU-Style FIFO Interface Operation Read Status Description
Note that bits 7 to 4 can be arbitrary values and that X= not used.
The timing of reading and writing in this mode is shown in Figure 4.21 and Table 4.8.
A0
CS#
WR#
RD#
D7..0
t2
t3
t1
Valid
Valid
t4
t6
Valid
t5
t7
Valid
Figure 4.21 CPU-Style FIFO Interface Operation Signal Waveforms.
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