Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.3
Clearance No.: FTDI #199
4.8 MPSSE Interface Mode Description.
MPSSE Mode is designed to allow the FT232H to interface efficiently with synchronous serial protocols
such as JTAG, I
2
C and SPI (MASTER) Bus. It can also be used to program SRAM based FPGA‟s over USB.
The MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous
serial protocol (industry standard or proprietary) to be implemented using the FT232H.
MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can
be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of
30 Mbits/s.
When the FT232H is configured in MPSSE mode, the IO timing and signals used are shown in
be provide a slower clock.
Figure 4.14 MPSSE Signal Waveforms
Name
t1
t2
t3
t4
t5
t6
Min
7.5
7.5
1
0
11
Typ
16.67
8.33
8.33
Max Units
15.15
ns
9.17
ns
9.17
ns
7.15
ns
ns
ns
Comments
CLKOUT period
CLKOUT high period
CLKOUT low period
CLKOUT to TDI/DO delay
TDI/DO hold time
TDI/DO setup time
Table 4.4 MPSSE Signal Timings
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