Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
Bit
Name
Type
Default value
Description
in the USB2.0 specification from the memory
to FIFO. Then, send the packet to the
transceiver.
TEST_K
1
0
TST_KSTA
TST_JSTA
R/W
R/W
1’b0
1’b0
Upon writing a ‘1,’ the D+/D- are set to the
high-speed K state.
TEST_J
Upon writing a ‘1,’ the D+/D- are set to the
high-speed J state.
Table 5-26 Test mode register
5.5.2 TESTPMSET1 register (address = 70h)
This parameter setting register is only used by test packet mode.
Bit
Name
Type
RO
Default value
7’b0
Description
-
[31:25]
[24: 8]
Reserved
DMA_LEN
R/W
11’h000
DMA Length
The total bytes of the DMA controller will
move. The maximum length is 1024 – 1 Bytes.
[7: 2]
1
Reserved
RO
6’b0
1’b0
-
DMA Type
DMA_TYPE
R/W
The transfer type of data moving
0: FIFO to Memory
1: Memory to FIFO
DMA Start
0
DMA_START
R/W
1’b0
This bit informs the DMA controller to initiate
the DMA transfer.
Table 5-27 Test mode parameter setting 1 register
5.5.3 TESTPMSET2 register (address = 74h)
This parameter setting register is only used by test packet mode.
Bit
Name
Type
Default value
Description
[31:0]
DMA_MADDR
R/W
32’b0
DMA Memory Address
The starting address of memory to request the
DMA transfer.
Table 5-28 Test parameter setting 2 register
Copyright © 2012 Future Technology Devices International Limited
39
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
