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DS_FT313H 参数 Datasheet PDF下载

DS_FT313H图片预览
型号: DS_FT313H
PDF下载: 下载PDF文件 查看货源
内容描述: 该FT313H是一个高速通用串行总线( USB )主机控制器,通用串行总线规范2.0版兼容,并支持高达480M bit / s的数据传输速度。 [The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s.]
分类和应用: 数据传输控制器
文件页数/大小: 64 页 / 1588 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000589  
FT313H USB2.0 HS Host Controller Datasheet Version 1.1  
Clearance No.: FTDI# 318  
Bit  
Name  
Type  
Default value Description  
disconnect  
Indicates that wake up event is triggered.  
The INT line will be asserted if the  
respective enable bit in the HCINTEN  
register is set.  
0: No wake up event has occurred on the  
port when device connects or disconnects.  
1: Wake up event has occurred on the port  
when device connects or disconnects.  
6
OCINT  
R/WC  
1’b0  
Overcurrent interrupt  
Indicates that overcurrent event is  
triggered. The INT line will be asserted if  
the respective enable bit in the HCINTEN  
register is set.  
0: No overcurrent event has occurred.  
1: Overcurrent event has occurred.  
5
CLKREADY  
R/WC  
1’b0  
Clock ready  
Indicates that internal clock signals are  
running stable. The INT line will be asserted  
if the respective enable bit in the HCINTEN  
register is set.  
0: No clock ready event has occurred.  
1: Clock ready event has occurred.  
4
3
BUSINACTIVE  
R/WC  
R/WC  
1’b0  
1’b0  
USB Bus inactive interrupt  
Indicates that USB bus is inactive. The INT  
line will be asserted if the respective enable  
bit in the HCINTEN register is set.  
0: USB bus is active.  
1: USB bus is inactive.  
REMOTEWKINT  
Remote Wake up interrupt  
Indicates INT was generated when the host  
controller remote wakeup. The INT line will  
be asserted if the respective enable bit in  
the HCINTEN register is set.  
0: No remote wake up.  
1: Remote wake up event occurred.  
2
1
DMAEOTINT  
R/WC  
R/WC  
1’b0  
1’b0  
DMA EOT interrupt  
Indicates the DMA transfer completion. The  
INT line will be asserted if the respective  
enable bit in the HCINTEN register is set.  
0: No DMA transfer is completed.  
1: DMA transfer is completed.  
SOFINT  
SOF interrupt  
The INT line will be asserted if the  
respective bit enable is set.  
Copyright © 2012 Future Technology Devices International Limited  
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