Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
4.3 NOR bus interface mode
The bus interface will be in NOR 16-bit mode, if pin ALE/ADV_N is HIGH and pin CLE is LOW,
when:
•
The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW.
Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in NOR 8-bit mode.
The NOR Flash interface access consists of two phases: address and data.
The address is valid when CS_N/CE_N and ADV_N are LOW, and the address is latched at the
rising edge of ADV_N. For a read operation, WE_N must be HIGH. OE_N is the data output
control. When active, the addressed register or the buffer data is driven to the I/O bus. The
read operation is completed when CS_N/CE_N is de-asserted. For a write operation, OE_N
must be HIGH. The WE_N assertion can start when ADV_N is de-asserted. WE_N is the data
input strobe signal. When de-asserted, data will be written to the addressed register or the
buffer. The write operation is completed when CS_N/CE_N is de-asserted.
4.4 General multiplex bus interface mode
The bus interface will be in general multiplex 16-bit mode, if pin ALE/ADV_N is LOW and pin
CLE is HIGH, when:
•
The CS_N/CE_N pin goes LOW, and the RD_N /RE_N/OE_N pin goes LOW.
Then, if the DATA_BUS_WIDTH bit is set, the bus interface will be in general multiplex 8-bit
mode. The general multiplex bus interface supports most advance application processors.
The general multiplex interface access consists of two phases: address and data.
The address is valid when ALE/ADV_N goes HIGH, and the address is latched at the falling
edge of ALE/ADV_N. For a read operation, WR_N/WE_N must be HIGH. RD_N /RE_N/OE_N is
the data output control. When active, the addressed register or the buffer data is driven to the
I/O bus. The read operation is completed when CS_N/CE_N is de-asserted. For a write
operation, RD_N /RE_N/OE_N must be HIGH. The WR_N/WE_N assertion can start when
ALE/ADV_N is de-asserted. WR_N/WE_N is the data input strobe signal. When de-asserted,
data will be written to the addressed register or the buffer. The write operation is completed
when CS_N/CE_N is de-asserted. The DMA transfer is also applicable to this interface.
4.5 Interface mode lock
The bus interface can be locked in any of the modes, SRAM, NOR, or general multiplex, using
bit 3 of the HW Mode Control register. To lock the interface in a particular mode:
1. Read bits 7 and 6 of the SW Reset register.
2. Set bit 3 of the HW Mode Control register to logic 1.
3. Read bits 7 and 6 of the SW Reset register to ensure that the interface is locked in the
desired mode.
Note: the default is 16-bit SRAM mode.
4.6 DMA controller
The DMA controller of the FT313H is used to transfer data between the system memory and
local buffers. It shares data bus AD[15:0] and control signals WR_N/WE_N, RD_N
/RE_N/OE_N, and CS_N/CE_N. The logic is dependent on the bus interface mode setting.
DREQ signal is from the FT313H to indicate the start of DMA transfer. DACK signal is used to
differentiate if data transferred is for the DMA or PIO access. When DACK is asserted, it
indicates that it is still in DMA mode. When DACK is de-asserted, it indicates that PIO is to be
accessed. ALE/ADV_N and CLE are ignored in a DMA access cycle. Correct data will be
captured only on the rising edge of WR_N/WE_N and RD_N /RE_N/OE_N.
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