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DS_FT313H 参数 Datasheet PDF下载

DS_FT313H图片预览
型号: DS_FT313H
PDF下载: 下载PDF文件 查看货源
内容描述: 该FT313H是一个高速通用串行总线( USB )主机控制器,通用串行总线规范2.0版兼容,并支持高达480M bit / s的数据传输速度。 [The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s.]
分类和应用: 数据传输控制器
文件页数/大小: 64 页 / 1588 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000589  
FT313H USB2.0 HS Host Controller Datasheet Version 1.1  
Clearance No.: FTDI# 318  
4 Function Description  
The FT313H is a USB2.0 compatible EHCI single port host controller which is mainly composed  
of the following:  
Microcontroller bus interface  
SRAM bus interface mode  
NOR bus interface mode  
General multiplex bus interface mode  
Interface mode lock  
DMA controller  
EHCI host controller  
System clock  
Power management  
BCD mode  
The functions for each block are briefly described in the following subsections.  
4.1 Microcontroller Bus Interface  
The FT313H has a fast advance general purpose interface to communicate with most types of  
microcontrollers and microprocessors. This microcontroller interface is configured using pins  
ALE/ADV_N and CLE to accommodate most types of interfaces. The bus interface supports 8-  
bit and 16-bit, which can be configured using bit DATA_BUS_WIDTH. Three bus interface types  
are selected using inputs ALE/ADV_N and CLE during power up, the RD_N /RE_N/OE_N and  
CS_N/CE_N pins, or the RESET_N pin. Table 4.1 provides detail of bus configuration for each  
mode. Table 4.2 shows pinout information of each bus interface.  
Bus Mode  
ALE/ADV_N  
CLE  
DATA_BUS  
_WIDTH  
Signal Description  
A[7:0]: 8-bit address bus  
AD[7:0]: 8-bit data bus  
SRAM 8-bit  
HIGH  
HIGH  
1
Write (WR_N), read (RD_N), chip  
select (CS_N): control signals for  
normal SRAM mode  
DACK: DMA acknowledge input  
DREQ: DMA request output  
A[7:0]: 8-bit address bus  
AD[15:0]: 16-bit data bus  
SRAM 16-bit  
HIGH  
HIGH  
0
Write (WR_N), read (RD_N), chip  
select (CS_N): control signals for  
normal SRAM mode  
DACK: DMA acknowledge input  
DREQ: DMA request output  
AD[7:0]: 8-bit data bus  
NOR 8-bit  
HIGH  
HIGH  
LOW  
LOW  
LOW  
HIGH  
1
0
1
ADV_N, write enable, output enable,  
chip select: control signals  
AD[15:0]: 16-bit data bus  
NOR 16-bit  
ADV_N, write enable, output enable,  
chip select: control signals  
AD[7:0]: 8-bit data bus  
ALE, write(WR_N), read(RD_N), chip  
General  
Multiplex 8-bit  
Copyright © 2012 Future Technology Devices International Limited  
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