CPM Electrical Characteristics
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 63. Ethernet Transmit Timing Diagram
12.9 SMC Transparent AC Electrical Specifications
Table 25 provides the SMC transparent timings as shown in Figure 64.
Table 25. SMC Transparent Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
150 SMCLK clock period 1
151 SMCLK width low
151A SMCLK width high
152 SMCLK rise/fall time
100
50
50
—
10
20
5
—
—
—
15
50
—
—
ns
ns
ns
ns
ns
ns
ns
153 SMTXD active delay (from SMCLK falling edge)
154 SMRXD/SMSYNC setup time
155 RXD1/SMSYNC hold time
1
SyncCLK must be at least twice as fast as SMCLK.
MPC885/MPC880 Hardware Specifications, Rev. 3
63
Freescale Semiconductor
FREESCALE [ Freescale ]
