CPM Electrical Characteristics
12.7 SCC in NMSI Mode Electrical Specifications
Table 22 provides the NMSI external clock timing.
Table 22. NMSI External Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
100 RCLK1 and TCLK1 width high 1
1/SYNCCLK
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
101 RCLK1 and TCLK1 width low
1/SYNCCLK + 5
102 RCLK1 and TCLK1 rise/fall time
—
15.00
50.00
50.00
—
103 TXD1 active delay (from TCLK1 falling edge)
104 RTS1 active/inactive delay (from TCLK1 falling edge)
105 CTS1 setup time to TCLK1 rising edge
106 RXD1 setup time to RCLK1 rising edge
107 RXD1 hold time from RCLK1 rising edge 2
108 CD1 setup time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
—
—
—
1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2 Also applies to CD and CTS hold time when they are used as external sync signals.
Table 23 provides the NMSI internal clock timing.
Table 23. NMSI Internal Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
100 RCLK1 and TCLK1 frequency 1
0.00
—
SYNCCLK/3
MHz
ns
102 RCLK1 and TCLK1 rise/fall time
—
30.00
30.00
—
103 TXD1 active delay (from TCLK1 falling edge)
104 RTS1 active/inactive delay (from TCLK1 falling edge)
105 CTS1 setup time to TCLK1 rising edge
106 RXD1 setup time to RCLK1 rising edge
107 RXD1 hold time from RCLK1 rising edge 2
108 CD1 setup time to RCLK1 rising edge
0.00
0.00
40.00
40.00
0.00
40.00
ns
ns
ns
—
ns
—
ns
—
ns
1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1.
2 Also applies to CD and CTS hold time when they are used as external sync signals
MPC885/MPC880 Hardware Specifications, Rev. 3
59
Freescale Semiconductor
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