CPM Electrical Characteristics
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 60. HDLC Bus Timing Diagram
12.8 Ethernet Electrical Specifications
Table 24 provides the Ethernet timings as shown in Figure 61 to Figure 63.
Table 24. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120 CLSN width high
121 RCLK1 rise/fall time
122 RCLK1 width low
123 RCLK1 clock period 1
124 RXD1 setup time
125 RXD1 hold time
40
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
80
20
5
120
—
—
126 RENA active delay (from RCLK1 rising edge of the last data bit)
127 RENA width low
10
100
—
—
—
128 TCLK1 rise/fall time
15
—
129 TCLK1 width low
40
99
—
130 TCLK1 clock period1
101
50
50
50
131 TXD1 active delay (from TCLK1 rising edge)
132 TXD1 inactive delay (from TCLK1 rising edge)
133 TENA active delay (from TCLK1 rising edge)
6.5
10
MPC885/MPC880 Hardware Specifications, Rev. 3
61
Freescale Semiconductor
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