CPM Electrical Characteristics
Table 24. Ethernet Timing (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
134 TENA inactive delay (from TCLK1 rising edge)
138 CLKO1 low to SDACK asserted 2
10
—
—
50
20
20
ns
ns
ns
139 CLKO1 low to SDACK negated 2
1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 61. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 62. Ethernet Receive Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
62
Freescale Semiconductor
FREESCALE [ Freescale ]
