Bus Signal Timing
Table 14 shows the reset timing for the MPC885/880.
Table 14. Reset Timing
33 MHz 40 MHz
66 MHz
80 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
CLKOUT to HRESET high
—
20.00
—
20.00
—
20.00
—
20.00
ns
R69 impedance
(MAX = 0.00 × B1 + 20.00)
CLKOUT to SRESET high
R70 impedance
—
20.00
—
—
20.00
—
—
20.00
—
—
20.00
—
ns
ns
(MAX = 0.00 × B1 + 20.00)
RSTCONF pulse width
(MIN = 17.00 × B1)
515.20
425.00
257.60
212.50
R71
R72
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
Configuration data to HRESET
504.50
425.00
277.30
237.50
R73 rising edge setup time
(MIN = 15.00 × B1 + 50.00)
Configuration data to RSTCONF 350.00
R74 rising edge setup time
—
—
350.00
0.00
0.00
—
—
—
350.00
0.00
0.00
—
—
—
350.00
0.00
0.00
—
—
—
ns
ns
ns
ns
ns
ns
(MIN = 0.00 × B1 + 350.00)
Configuration data hold time after 0.00
R75 RSTCONF negation
(MIN = 0.00 × B1 + 0.00)
Configuration data hold time after 0.00
R76 HRESET negation
—
—
—
—
(MIN = 0.00 × B1 + 0.00)
HRESET and RSTCONF
R77 asserted to data out drive
(MAX = 0.00 × B1 + 25.00)
—
—
—
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
RSTCONF negated to data out
R78 high impedance
—
—
—
(MAX = 0.00 × B1 + 25.00)
CLKOUT of last rising edge
before chip three-states
R79 HRESET to data out high
impedance
—
—
—
(MAX = 0.00 × B1 + 25.00)
DSDI, DSCK setup
R80
90.90
0.00
—
—
—
75.00
0.00
—
—
—
45.50
0.00
—
—
—
37.50
0.00
—
—
—
ns
ns
ns
(MIN = 3.00 × B1)
DSDI, DSCK hold time
R81
(MIN = 0.00 × B1 + 0.00)
SRESET negated to CLKOUT
R82 rising edge for DSDI and DSCK
sample (MIN = 8.00 × B1)
242.40
200.00
121.20
100.00
MPC885/MPC880 Hardware Specifications, Rev. 3
42
Freescale Semiconductor
FREESCALE [ Freescale ]
