Bus Signal Timing
Table 13 shows the debug port timing for the MPC885/880.
Table 13. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
DSCK cycle time
3 × TCLOCKO
-
-
D61
D62
UT
DSCK clock pulse width
1.25 × TCLO
CKOUT
D63 DSCK rise and fall times
0.00
8.00
5.00
0.00
0.00
3.00
ns
ns
ns
ns
ns
D64 DSDI input data setup time
D65 DSDI data hold time
D66 DSCK low to DSDO data valid
D67 DSCK low to DSDO invalid
15.00
2.00
Figure 32 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
Figure 32. Debug Port Clock Input Timing
Figure 33 provides the timing for the debug port.
D63
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 33. Debug Port Timings
MPC885/MPC880 Hardware Specifications, Rev. 3
41
Freescale Semiconductor
FREESCALE [ Freescale ]
