Bus Signal Timing
Table 11 shows the PCMCIA timing for the MPC885/880.
Table 11. PCMCIA Timing
33 MHz 40 MHz
66 MHz
80 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
A(0:31), REG valid to PCMCIA
20.70
—
16.70
—
9.40
—
7.40
—
ns
P44 strobe asserted 1
(MIN = 0.75 × B1 – 2.00)
A(0:31), REG valid to ALE
28.30
—
23.00
—
13.20
—
10.50
—
ns
P45 negation1
(MIN = 1.00 × B1 – 2.00)
CLKOUT to REG valid
(MAX = 0.25 × B1 + 8.00)
7.60
8.60
7.60
7.60
—
15.60
—
6.30
7.30
6.30
6.30
—
14.30
—
3.80
4.80
3.80
3.80
—
11.80
—
3.13
4.13
3.13
3.13
—
11.13
—
ns
ns
ns
ns
ns
P46
P47
P48
P49
CLKOUT to REG invalid
(MIN = 0.25 – B1 + 1.00)
CLKOUT to CE1, CE2 asserted
(MAX = 0.25 × B1 + 8.00)
15.60
15.60
11.00
14.30
14.30
11.00
11.80
11.80
11.00
11.13
11.13
11.00
CLKOUT to CE1, CE2 negated
(MAX = 0.25 × B1 + 8.00)
CLKOUT to PCOE, IORD,
P50 PCWE, IOWR assert time
(MAX = 0.00 × B1 + 11.00)
CLKOUT to PCOE, IORD,
P51 PCWE, IOWR negate time
(MAX = 0.00 × B1 + 11.00)
2.00
11.00
2.00
11.00
2.00
11.00
2.00
11.00
ns
CLKOUT to ALE assert time
P52
7.60
—
13.80
15.60
—
6.30
—
12.50
14.30
—
3.80
—
10.00
11.80
—
3.13
—
9.40
11.13
—
ns
ns
ns
(MAX = 0.25 × B1 + 6.30)
CLKOUT to ALE negate time
P53
(MAX = 0.25 × B1 + 8.00)
PCWE, IOWR negated to
P54 D(0:31) invalid 1
5.60
4.30
1.80
1.13
(MIN = 0.25 × B1 – 2.00)
WAITA and WAITB valid to
P55 CLKOUT rising edge1
(MIN = 0.00 × B1 + 8.00)
8.00
2.00
—
—
8.00
2.00
—
—
8.00
2.00
—
—
8.00
2.00
—
—
ns
ns
CLKOUT rising edge to WAITA
P56 and WAITB invalid1
(MIN = 0.00 × B1 + 2.00)
1 PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC Family User’s Manual.
MPC885/MPC880 Hardware Specifications, Rev. 3
37
Freescale Semiconductor
FREESCALE [ Freescale ]
