Bus Signal Timing
Figure 20 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 20. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing
Figure 21 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 21. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
34
Freescale Semiconductor
FREESCALE [ Freescale ]
