Bus Signal Timing
Figure 11 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31]
Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 12 through Figure 15 provide the timing for the external bus read controlled by various GPCM factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22
B23
B25
B26
B19
OE
B28
WE[0:3]
D[0:31]
B18
Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00)
MPC885/MPC880 Hardware Specifications, Rev. 3
27
Freescale Semiconductor
FREESCALE [ Freescale ]
