Bus Signal Timing
Figure 9 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
B17
B17
TA, BI
B16
TEA, KR,
RETRY, CR
B16
BB, BG, BR
Figure 9. Synchronous Input Signals Timing
Figure 10 provides normal case timing for input data. It also applies to normal read accesses under the control of the
user-programmable machine (UPM) in the memory controller.
CLKOUT
B16
B17
TA
B18
B19
D[0:31]
Figure 10. Input Data Timing in Normal Case
MPC885/MPC880 Hardware Specifications, Rev. 3
26
Freescale Semiconductor