Bus Signal Timing
Figure 5 provides the control timing diagram.
2.0 V
2.0 V
CLKOUT
0.8 V
0.8 V
A
B
2.0 V
2.0 V
0.8 V
Outputs
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
D
C
2.0 V
0.8 V
2.0 V
0.8 V
Inputs
D
C
2.0 V
0.8 V
2.0 V
0.8 V
Inputs
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 5. Control Timing
Figure 6 provides the timing for the external clock.
CLKOUT
B1
B1
B3
B2
B4
B5
Figure 6. External Clock Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
24
Freescale Semiconductor
FREESCALE [ Freescale ]
