Package Description
18.3 Pinout Listings
NOTE
The DMA_DACK[0:1] and TEST_SEL/TEST_SEL pins must be set to a
proper state during POR configuration. Please refer to the pinlist table of the
individual device for more details.
For MPC8548/47/45, GPIOs are still available on
PCI1_AD[63:32]/PC2_AD[31:0] pins if they are not used for PCI
functionality.
For MPC8545/43, eTSEC does not support 16 bit FIFO mode.
Table 67 provides the pinout listing for the MPC8548E 783 FC-PBGA package.
Table 67. MPC8548E Pinout Listing
Power
Supply
Signal
Package Pin Number
Pin Type
Notes
PCI1 and PCI2 (One 64-Bit or Two 32-Bit)
PCI1_AD[63:32]/PCI2_AD[31:0]
AB14, AC15, AA15, Y16, W16, AB16, AC16,
AA16, AE17, AA18, W18, AC17, AD16, AE16,
Y17, AC18, AB18, AA19, AB19, AB21, AA20,
AC20, AB20, AB22, AC22, AD21, AB23, AF23,
AD23, AE23, AC23, AC24
I/O
OV
OV
17
DD
DD
PCI1_AD[31:0]
AH6, AE7, AF7, AG7, AH7, AF8, AH8, AE9,
AH9, AC10, AB10, AD10, AG10, AA10, AH10,
AA11, AB12, AE12, AG12, AH12, AB13, AA12,
AC13, AE13, Y14, W13, AG13, V14, AH13,
AC14, Y15, AB15
I/O
17
PCI1_C_BE[7:4]/PCI2_C_BE[3:0]
PCI1_C_BE[3:0]
PCI1_PAR64/PCI2_PAR
PCI1_GNT[4:1]
PCI1_GNT0
AF15, AD14, AE15, AD15
I/O
I/O
I/O
O
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
17
17
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
AF9, AD11, Y12, Y13
W15
AG6, AE6, AF5, AH5
5, 9, 35
AG5
AF11
AD12
AC12
V13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
2
PCI1_IRDY
PCI1_PAR
—
2
PCI1_PERR
PCI1_SERR
2, 4
2
PCI1_STOP
W12
PCI1_TRDY
AG11
2
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
89
FREESCALE [ Freescale ]
