欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
 浏览型号MPC8543EVUAQG的Datasheet PDF文件第4页浏览型号MPC8543EVUAQG的Datasheet PDF文件第5页浏览型号MPC8543EVUAQG的Datasheet PDF文件第6页浏览型号MPC8543EVUAQG的Datasheet PDF文件第7页浏览型号MPC8543EVUAQG的Datasheet PDF文件第9页浏览型号MPC8543EVUAQG的Datasheet PDF文件第10页浏览型号MPC8543EVUAQG的Datasheet PDF文件第11页浏览型号MPC8543EVUAQG的Datasheet PDF文件第12页  
Overview  
— Memory prefetching of PCI read accesses  
— Supports posting of processor-to-PCI and PCI-to-memory writes  
— PCI 3.3-V compatible  
— Selectable hardware-enforced coherency  
Serial RapidIO™ interface unit  
— Supports RapidIO™ Interconnect Specification, Revision 1.2  
— Both 1× and 4× LP-serial link interfaces  
— Long- and short-haul electricals with selectable pre-compensation  
— Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane  
— Auto detection of 1×- and 4×-mode operation during port initialization  
— Link initialization and synchronization  
— Large and small size transport information field support selectable at initialization time  
— 34-bit addressing  
— Up to 256 bytes data payload  
— All transaction flows and priorities  
— Atomic set/clr/inc/dec for read-modify-write operations  
— Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at  
a remote memory system  
— Receiver-controlled flow control  
— Error detection, recovery, and time-out for packets and control symbols as required by the  
RapidIO specification  
— Register and register bit extensions as described in part VIII (Error Management) of the  
RapidIO specification  
— Hardware recovery only  
— Register support is not required for software-mediated error recovery.  
— Accept-all mode of operation for fail-over support  
— Support for RapidIO error injection  
— Internal LP-serial and application interface-level loopback modes  
— Memory and PHY BIST for at-speed production test  
RapidIO-compatible message unit  
— 4 Kbytes of payload per message  
— Up to sixteen 256-byte segments per message  
— Two inbound data message structures within the inbox  
— Capable of receiving three letters at any mailbox  
— Two outbound data message structures within the outbox  
— Capable of sending three letters simultaneously  
— Single segment multicast to up to 32 devIDs  
— Chaining and direct modes in the outbox  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
8
Freescale Semiconductor  
 复制成功!