PCI Express
V
= 0 mV
V
= 0 mV
TX-DIFF
RX-DIFF
(D+ D– Crossing Point)
(D+ D– Crossing Point)
[Transition Bit]
= 800 mV
V
TX-DIFFp-p-MIN
[De-Emphasized Bit]
566 mV (3 dB) >= >= 505 mV (4 dB)
V
TX-DIFFp-p-MIN
0.07 UI = UI – 0.3 UI (J
)
TX-TOTAL-MAX
[Transition Bit]
= 800 mV
V
TX-DIFFp-p-MIN
Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications
16.4.3 Differential Receiver (RX) Input Specifications
Table 53 defines the specifications for the differential input at all receivers (RXs). The parameters are
specified at the component pins.
Table 53. Differential Receiver (RX) Input Specifications
Symbol
Parameter
Min
Nom
Max
Unit
Comments
UI
Unit interval
399.88
400
400.12
ps Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations.
See Note 1.
V
Differential
peak-to-peak
input voltage
0.175
0.4
—
—
1.200
—
V
V
= 2 × |V
– V
|. See Note 2.
RX-D–
RX-DIFFp-p
RX-DIFFp-p
RX-D+
T
Minimum
receiver eye
width
UI The maximum interconnect media and transmitter
jitter that can be tolerated by the receiver can be
RX-EYE
derived as T
= 1 – T
= 0.6 UI.
RX-MAX-JITTER
RX-EYE
See Notes 2 and 3.
T
Maximum time
between the
jittermedian and
maximum
deviation from
the median
—
—
0.3
UI Jitter is defined as the measurement variation of
RX-EYE-MEDIAN-to-
MAX-JITTER
the crossing points (V = 0 V) in relation
RX-DIFFp-p
to a recovered TX UI. A recovered TX UI is
calculated over 3500 consecutive unit intervals of
sample data. Jitter is measured using all edges of
the 250 consecutive UI in the center of the
3500 UI used for calculating the TX UI.
See Notes 2, 3, and 7.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
73
FREESCALE [ Freescale ]
