PCI Express
V
RX-DIFF
= 0 mV
(D+ D– Crossing Point)
[Transition Bit]
V
TX-DIFFp-p-MIN
= 800 mV
V
TX-DIFF
= 0 mV
(D+ D– Crossing Point)
[De-Emphasized Bit]
566 mV (3 dB) >=
V
TX-DIFFp-p-MIN
>= 505 mV (4 dB)
0.07 UI = UI – 0.3 UI (J
TX-TOTAL-MAX
)
[Transition Bit]
V
TX-DIFFp-p-MIN
= 800 mV
Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications
16.4.3
Differential Receiver (RX) Input Specifications
defines the specifications for the differential input at all receivers (RXs). The parameters are
specified at the component pins.
Table 53. Differential Receiver (RX) Input Specifications
Symbol
UI
Parameter
Unit interval
Min
399.88
Nom
400
Max
400.12
Unit
ps
Comments
Each UI is 400 ps ± 300 ppm. UI does not account
for spread spectrum clock dictated variations.
See Note 1.
V
RX-DIFFp-p
= 2 × |V
RX-D+
– V
RX-D–
|. See Note 2.
V
RX-DIFFp-p
Differential
peak-to-peak
input voltage
Minimum
receiver eye
width
Maximum time
between the
jitter median and
maximum
deviation from
the median
0.175
—
1.200
V
T
RX-EYE
0.4
—
—
UI
The maximum interconnect media and transmitter
jitter that can be tolerated by the receiver can be
derived as T
RX-MAX-JITTER
= 1 – T
RX-EYE
= 0.6 UI.
See Notes 2 and 3.
Jitter is defined as the measurement variation of
the crossing points (V
RX-DIFFp-p
= 0 V) in relation
to a recovered TX UI. A recovered TX UI is
calculated over 3500 consecutive unit intervals of
sample data. Jitter is measured using all edges of
the 250 consecutive UI in the center of the
3500 UI used for calculating the TX UI.
See Notes 2, 3, and 7.
T
RX-EYE-MEDIAN-to-
MAX-JITTER
—
—
0.3
UI
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
73
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
