JTAG
11.3.2.1
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
CLK_DELAY
+ t
DATA_DELAY
+ t
ODLY
+ t
SHSIVKH
< 1.5
×
t
SHSCK
t
CLK_DELAY
+ t
DATA_DELAY
< 1.5
×
t
SHSCK
–
t
ODLY
–
t
SHSIVKH
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
t
CLK_DELAY
+ t
DATA_DELAY
< 30
–
14
–
5
t
CLK_DELAY
+ t
DATA_DELAY
< 11
11.3.2.2
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5
×
t
SHSCK
< t
CLK_DELAY
+ t
DATA_DELAY
+ t
OH
–
t
SHSIXKH
+ t
INT_CLK_DLY
0.5
×
t
SHSCK
–
t
OH
+ t
SHSIXKH
–
t
INT_CLK_DLY
< t
CLK_DELAY
+ t
DATA_DELAY
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10
–
2.5 + (-1.5) < t
CLK_DELAY
+ t
DATA_DELAY
6 < t
CLK_DELAY
+ t
DATA_DELAY
11.3.2.3
High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5
×
t
SHSCK
–
t
OH
+ t
SHSIXKH
< t
CLK_DELAY
+ t
DATA_DELAY
< 1.5
×
t
SHSCK
–
t
ODLY
–
t
SHSIVKH
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the MPC8378E.
12.1
JTAG DC Electrical Characteristics
provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the
MPC8378E.
Table 48. JTAG interface DC Electrical Characteristics
Parameter
Input high voltage
Input low voltage
Input current
Symbol
V
IH
V
IL
I
IN
Condition
—
—
—
Min
2.5
–0.3
—
Max
OV
DD
+ 0.3
0.8
±30
Unit
V
V
μA
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
56
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
