Enhanced Secure Digital Host Controller (eSDHC)
This means that data delay should be equal or less than the clock delay in the ideal case where
= 10 ns:
t
SHSCLKL
t
t
– t
DATA_DELAY CLK_DELAY
< 10 – 6 – 4
– t
DATA_DELAY CLK_DELAY
< 0
11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
t
t
< t
+ t + t
SHSKHOX
– t
DATA_DELAY IH
CLK_DELAY
SHSCKL
– t
CLK_DELAY DATA_DELAY
< t
+ t
– t
SHSKHOX IH
SHSCKL
This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of
= 10 ns:
t
SHSCLKL
t
t
– t
CLK_DELAY DATA_DELAY
< 10 + 0 – 2
– t
CLK_DELAY DATA_DELAY
< 8
11.3.2 High-Speed Input Path (Read)
Figure 35 provides the data and command input timing diagram.
t
(Clock Cycle)
SHSCK
1/2 Cycle
Wrong Edge
Right Edge
SD CLK at the
MPC8378E Pin
Sampling
Edge
t
CLK_DELAY
Driving
Edge
SD CLK at
the Card Pin
t
ODLY
t
t
DATA_DELAY
OH
Output from the
SD Card Pins
Input at the
MPC8378E Pins
t
(MPC8378E Input Hold)
SHSIVKH
(MPC8378E Input Setup)
t
SHSIXKH
Figure 35. High Speed Input Path
For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was
driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a
sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal
clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample
the data, and therefore used in the equations.
™
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
55
FREESCALE [ Freescale ]
