Clocking
Table 73. CSB Frequency Options for Agent Mode (continued)
Input Clock
Frequency (MHz)
2
25
csb_clk
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
1
2
CFG_CLKIN_DIV
at reset
1
SPMF
csb_clk
:
Input Clock
Ratio
2
33.33
Frequency (MHz)
200
233
266
300
333
66.67
—
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
6:1
7:1
8:1
9:1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
150
175
200
225
250
275
300
325
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
22.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in
should be considered as reserved.
NOTE
Core VCO frequency = core frequency
×
VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
Table 74. e300 Core PLL Configuration
RCWL[COREPLL]
VCO Divider
1
core_clk
:
csb_clk
Ratio
0–1
nn
2–5
0000
6
0
PLL bypassed
(PLL off,
csb_clk
clocks
core directly)
n/a
1:1
1:1
1:1
PLL bypassed
(PLL off,
csb_clk
clocks
core directly)
n/a
2
4
8
11
00
01
10
nnnn
0001
0001
0001
n
0
0
0
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
111
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
