Clocking
As shown in
the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The
csb_clk
frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk
= {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The
csb_clk
serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the
csb_clk
frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the
MPC8379E Reference Manual
for more information on the clock
subsystem.
The internal
ddr_clk
frequency is determined by the following equation:
ddr_clk
=
csb_clk
× (1 + RCWL[DDRCM])
Note that
ddr_clk
is not the external memory bus frequency;
ddr_clk
passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as
ddr_clk.
The internal
lbiu_clk
frequency is determined by the following equation:
lbiu_clk
=
csb_clk
× (1 + RCWL[LBCM])
Note that
lbiu_clk
is not the external local bus frequency;
lbiu_clk
passes through the LBIU clock divider
to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by
LCCR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the
csb_clk
frequency. Those units have a default clock ratio that can be configured by a memory mapped register after
the device comes out of reset.
specifies which units have a configurable clock frequency.
Table 68. Configurable Clock Units
Unit
eTSEC1, eTSEC2
eSDHC and I
2
C1
1
Security block
USB DR
PCI and DMA complex
PCI Express1, 2
1
Default
Frequency
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk
csb_clk/3
Options
Off,
csb_clk, csb_clk/2, csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
Off,
csb_clk
Off, csb_clk,
csb_clk/2, csb_clk/3
This only applies to I
2
C1 (I
2
C2 clock is not configurable).
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
107
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
