Clocking
22 Clocking
shows the internal distribution of clocks within the MPC8378E.
e300 core
Core PLL
core_clk
csb_clk
to DDR
memory
controller
System PLL
ddr_clk
Clock
Unit
lbiu_clk
DDR
Clock
Div
/2
6
6
MCK[0:5]
MCK[0:5]
DDR
Memory
Device
/n
to local bus
memory
LBIU
controller
DLL
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
PCI_CLK/
PCI_SYNC_IN
Local Bus
Memory
Device
csb_clk
to rest
of the device
CFG_CLKIN_DIV
CLKIN
PCI Clock
Divider
5
PCI_SYNC_OUT
PCI_CLK[0:4]
Figure 67. MPC8378E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN signal should be tied to GND.
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
106
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
