Power Characteristics
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins will actively
be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the core voltages (V
DD
and AV
DD
) before the I/O voltages and
assert PORESET before the power supplies fully ramp up. V
DD
and AV
DD
must reach 90% of their
nominal value before GV
DD
, LV
DD
, and OV
DD
reach 10% of their value, see
I/O voltage
supplies, GV
DD
, LV
DD
, and OV
DD
do not have any ordering requirements with respect to one another.
V
I/O Voltage (GVDD, LVDD, and OVDD)
Core Voltage (VDD
,
AVDD)
90%
0.7 V
0
t
Figure 3. Power-Up Sequencing Example
Please note that the SerDes power supply (L[1,2]_nV
DD
) should follow the same timing as the core supply
(V
DD
).
The opposite sequence applies to the power down requirements. The I/O supplies must go down first and
immediately followed by the core and PLL supplies.
3
Power Characteristics
Table 5. MPC8378E Power Dissipation
1
The estimated typical power dissipation for the MPC8378E device is shown in
Table 5.
Core Frequency CSB/DDR Frequency
Sleep Power
Typical Application Typical Application Max Application
(MHz)
(MHz)
at T
j
= 65°C (W)
at T
j
= 65°C (W)
at T
j
= 125°C (W)
at T
j
= 125°C (W)
333
333
167
400
400
266
1.45
1.9
3.1
3.8
1.45
1.45
1.8
2.0
3.0
3.3
3.6
4.0
1.45
1.9
3.2
3.8
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
10
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
