Clock Input Timing
Table 6. MPC8378E Typical I/O Power Dissipation (continued)
Interface
Parameter
MII or RMII
GV
DD
(1.8 V)
—
GV
DD
/LBV
DD
(2.5 V)
—
OV
DD
LV
DD
LV
DD
L[1,2]_nV
DD
(3.3 V) (3.3 V) (2.5 V)
(1.0 V)
—
0.02
—
—
Unit
W
Comments
Multiply by
number of
interfaces used.
—
—
—
eTSEC I/O
SGMII
Load =
25 pf
RGMII or
RTBI
USB
(60MHz
Clock)
SerDes
Other I/O
12 Mbps
480 Mbps
per lane
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.01
0.2
—
—
—
—
—
—
0.05
—
—
—
—
0.029
—
—
—
0.029
—
W
W
W
W
W
W
—
—
0.01
—
Note:
The values given are for typical, and not worst case, switching.
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8378E. Note that
the PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on
whether the device is configured as a host or agent device. CLKIN is used when the device is in host mode.
4.1
DC Electrical Characteristics
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
—
—
0 V
≤V
IN
≤
OV
DD
0 V
≤V
IN
≤
0.5 V or
OV
DD
– 0.5 V
≤V
IN
≤
OV
DD
Symbol
V
IH
V
IL
I
IN
I
IN
Min
2.7
–0.3
—
—
Max
OV
DD
+ 0.3
0.4
± 10
± 30
Unit
V
V
μA
μA
Notes
—
—
provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
Input high voltage
Input low voltage
CLKIN Input current
PCI_CLK Input current
1
Note:
In PCI agent mode, this specification does not comply with
PCI 2.3 Specification.
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
13