System Design Information
capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA
system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system
designer should place at least one decoupling capacitor at each V , OV , GV , and LV pin of the
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device. These capacitors should receive their power from separate V , OV , GV , LV , and GND
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power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under
the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the V , OV , GV ,
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and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
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have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
21.4 Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OV , GV , or LV as required. Unused active high inputs should be
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connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of
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the MPC8347EA.
21.5 Output Buffer DC Impedance
The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the
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driver is a push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
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or GND. Then the value of each resistor is varied until the pad voltage is OV /2 (see Figure 44). The
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output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
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Freescale Semiconductor
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