Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8347E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.
1 Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8347EA.
e300 Core
DUART
Dual I2C
DDR
Timers
GPIO
Interrupt
Controller
32KB
32KB
I-Cache
SDRAM
Security
Local Bus
D-Cache
Controller
High-Speed
USB 2.0
10/100/1000
Ethernet
10/100/1000
Ethernet
SEQ
PCI
DMA
Dual
Role
Host
Figure 1. MPC8347EA Block Diagram
Major features of the device are as follows:
• Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
•
Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
2
Freescale Semiconductor
FREESCALE [ Freescale ]
