Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco_t_DMX32 DCO output
frequency
Low range (DRS = 00)
732 × ffll_ref
—
23.99
—
MHz
5, 6
Mid range (DRS = 01)
1464 × ffll_ref
—
—
—
47.97
180
—
—
—
1
MHz
ps
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
7
8
tfll_acquire FLL target frequency acquisition time
ms
PLL
fvco
Ipll
VCO operating frequency
PLL operating current
48.0
—
—
100
—
MHz
µA
9
9
1060
• PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2
MHz, VDIV multiplier = 48)
Ipll
PLL operating current
—
600
—
—
µA
• PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2
MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
10
10
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
11
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
26
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
