Pinout
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 17. Pin availability by package pin-count
Pin Number
44-LQFP
Lowest Priority <-- --> Highest
64-QFP/
LQFP
32-LQFP
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
2
1
2
PTD11
PTD01
PTH7
PTH6
PTE7
PTH2
—
KBI1_P1
FTM2_CH3
SPI1_MOSI
—
2
KBI1_P0
FTM2_CH2
SPI1_SCK
—
—
3
—
—
3
—
—
—
—
3
—
—
—
4
—
—
FTM2_CLK
BUSOUT
—
—
—
5
—
—
FTM1_CH1
FTM1_CH0
VDD
6
4
—
—
7
5
—
—
8
6
4
—
—
—
VDDA
VREFH2
VREFL
VSS3
9
7
5
—
—
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8
6
—
—
—
VSSA
9
7
PTB7
PTB6
—
—
I2C0_SCL
I2C0_SDA
—
—
EXTAL
XTAL
10
11
—
—
—
—
12
13
14
15
16
17
18
19
20
—
8
—
—
—
—
—
—
—
9
—
—
—
VSS
PTH11
PTH01
PTE6
PTE5
PTB51
PTB41
PTC3
PTC2
PTD7
PTD6
PTD5
PTC1
PTC0
PTF7
FTM2_CH1
FTM2_CH0
—
—
—
—
—
—
—
—
—
—
—
—
—
FTM2_CH5
FTM2_CH4
FTM2_CH3
FTM2_CH2
KBI1_P7
KBI1_P6
KBI1_P5
—
SPI0_PCS0
SPI0_MISO
—
ACMP1_OUT
—
10
11
12
—
—
—
13
14
—
NMI
—
—
—
—
—
—
—
—
ACMP1_IN2
ADC0_SE11
ADC0_SE10
—
—
UART2_TX
UART2_RX
—
—
—
FTM2_CH1
FTM2_CH0
—
ADC0_SE9
ADC0_SE8
ADC0_SE15
—
—
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
31
FREESCALE [ Freescale ]
