Pinout
2. VREFH and VDDA are internally connected.
3. VSSA and VSS are internally connected.
4. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. Table 17
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
8.2 Device pin assignment
2
2
1
1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTA2
PTA3
PTD1
PTD0
PTH7
PTH6
3
PTD2
PTD3
PTD4
PTF0
PTF1
VDD
4
PTE7
5
6
PTH2
VDD
7
8
VDDA/VREFH
VREFL
9
VSS
VSSA/VSS
10
11
12
13
14
15
16
PTE4
PTA6
PTA7
PTF2
PTF3
PTB0
PTB1
PTB7
PTB6
VSS
1
PTH1
1
PTH0
PTE6
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 21. 64-pin QFP/LQFP packages
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
33
FREESCALE [ Freescale ]
