Peripheral operating requirements and behaviors
Table 16. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in .
2
3
4
5
6
7
8
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
4 x tBus
—
—
ns
tBus
tBus
ns
tBus = 1/fBus
1
1
—
—
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
15
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
25
—
ns
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
13
13
4
SPSCK
(CPOL 0)
=
(INPUT)
5
5
3
12
SPSCK
=
(CPOL 1)
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
see
SEE
NOTE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
7
note
6
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
29
FREESCALE [ Freescale ]
