Peripheral operating requirements and behaviors
6.4.2 Analog comparator (ACMP) electricals
Table 14. Comparator electrical specifications
C
D
T
Characteristic
Supply voltage
Symbol
VDDA
IDDA
VAIN
VAIO
VH
Min
2.7
Typical
—
Max
5.5
20
Unit
V
Supply current (Operation mode)
Analog input voltage
—
10
µA
V
D
P
C
C
T
VSS - 0.3
—
—
VDDA
40
Analog input offset voltage
Analog comparator hysteresis (HYST=0)
Analog comparator hysteresis (HYST=1)
Supply current (Off mode)
Propagation Delay
—
mV
mV
mV
nA
µs
—
15
20
VH
—
20
30
IDDAOFF
tD
—
60
—
C
—
0.4
1
6.5 Communication interfaces
6.5.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high-drive strength is enabled for SPI output pins.
Table 15. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
2 x tBus
2048 x tBus
ns
tSPSCK
tSPSCK
ns
tBus = 1/fBus
1/2
—
—
—
—
—
—
—
—
—
4
1/2
—
5
tWSPSCK Clock (SPSCK) high or low time
tBus – 30
1024 x tBus
6
tSU
tHI
tv
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
15
0
—
—
ns
7
ns
8
—
0
25
ns
9
tHO
tRI
—
ns
10
—
tBus – 25
ns
Table continues on the next page...
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Freescale Semiconductor, Inc.
27
FREESCALE [ Freescale ]
