General
Table 7. Capacitance attributes (continued)
Symbol
CIN_D
Description
Input capacitance: digital pins
Min.
Max.
Unit
—
7
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
72
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
Bus clock
—
—
—
50
25
25
MHz
MHz
MHz
fFLASH
fLPTMR
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fERCLK
fLPTMR_pin
Flash clock
1
External reference clock
LPTMR clock
16
25
16
8
fLPTMR_ERCLK LPTMR external reference clock
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I2C signals.
K51 Sub-Family Data Sheet, Rev. 2, 4/2012.
20
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
