Pinout
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
A1
B1
1
2
PTE0
DISABLED
DISABLED
PTE0
UART1_TX
UART1_RX
RTC_CLKOUT
PTE1/
PTE1/
LLWU_P0
LLWU_P0
C5
C4
E1
D1
E2
D2
G1
F1
G2
F2
F4
G4
G3
F3
H1
3
4
VDD
VDD
VDD
VSS
VSS
VSS
5
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
6
7
8
9
10
11
12
13
14
15
16
17
VREFH
VREFH
VREFH
VREFL
VREFL
VREFL
VSSA
VSSA
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
H2
18
CMP1_IN3/
ADC0_SE23
CMP1_IN3/
ADC0_SE23
CMP1_IN3/
ADC0_SE23
H3
H4
H5
D3
19
20
21
22
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
PTA1
UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5
FTM0_CH6
JTAG_TCLK/
SWD_CLK
EZP_CLK
EZP_DI
D4
23
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
UART0_RX
JTAG_TDI
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
56
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
