Pinout
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
B8
A8
A7
B6
49
PTC4/
LLWU_P8
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
CMP1_OUT
CMP0_OUT
I2S0_MCLK
50
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_
ALT2
51
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_EXTRG I2S0_RX_
BCLK
52
PTC7
PTC7
USB_SOF_
OUT
I2S0_RX_FS
A6
B5
53
54
PTC8
PTC9
CMP0_IN2
CMP0_IN3
CMP0_IN2
CMP0_IN3
PTC8
PTC9
I2S0_MCLK
I2S0_RX_
BCLK
B4
A5
55
56
PTC10
DISABLED
DISABLED
PTC10
I2S0_RX_FS
PTC11/
PTC11/
LLWU_P11
LLWU_P11
C3
A4
C2
57
58
59
PTD0/
LLWU_P12
DISABLED
ADC0_SE5b
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART2_RTS_
b
PTD1
ADC0_SE5b
PTD1
UART2_CTS_
b
PTD2/
PTD2/
UART2_RX
LLWU_P13
LLWU_P13
B3
A3
60
61
PTD3
DISABLED
DISABLED
PTD3
SPI0_SIN
UART2_TX
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_
b
FTM0_CH4
FTM0_CH5
EWM_IN
C1
62
PTD5
ADC0_SE6b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI0_PCS2
UART0_CTS_
b/
UART0_COL_
b
EWM_OUT_b
B2
A2
63
64
PTD6/
LLWU_P15
ADC0_SE7b
DISABLED
PTD6/
LLWU_P15
SPI0_PCS3
CMT_IRO
UART0_RX
FTM0_CH6
FTM0_CH7
FTM0_FLT0
FTM0_FLT1
PTD7
PTD7
UART0_TX
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
58
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
