Pinout
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
E5
24
PTA2
JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_SWO
EZP_DO
D5
G5
F5
25
26
27
28
29
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_
b
FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM1_CH0
FTM1_CH1
JTAG_TMS/
SWD_DIO
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
PTA5
DISABLED
DISABLED
DISABLED
PTA5
USB_CLKIN
I2S0_TX_
BCLK
JTAG_TRST_
b
H6
G6
PTA12
PTA12
I2S0_TXD0
FTM1_QD_
PHA
PTA13/
LLWU_P4
PTA13/
LLWU_P4
I2S0_TX_FS
FTM1_QD_
PHB
G7
H7
H8
G8
30
31
32
33
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
LPTMR0_
ALT1
F8
F7
34
35
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
F6
E7
E8
36
37
38
PTB1
PTB2
PTB3
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
PTB2
PTB3
FTM1_QD_
PHB
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
UART0_RTS_
b
FTM0_FLT3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
UART0_CTS_
b/
FTM0_FLT0
UART0_COL_
b
E6
D7
D6
39
40
41
PTB16
PTB17
PTB18
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
UART0_RX
UART0_TX
EWM_IN
EWM_OUT_b
I2S0_TX_
BCLK
C7
D8
42
43
PTB19
PTC0
TSI0_CH12
TSI0_CH12
PTB19
PTC0
I2S0_TX_FS
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_EXTRG
C6
B7
44
45
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_
b
FTM0_CH0
FTM0_CH1
I2S0_TXD0
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
UART1_CTS_
b
I2S0_TX_FS
C8
46
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
I2S0_TX_
BCLK
E3
E4
47
48
VSS
VDD
VSS
VDD
VSS
VDD
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
57
FREESCALE [ Freescale ]
