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MK20DX64VLH5 参数 Datasheet PDF下载

MK20DX64VLH5图片预览
型号: MK20DX64VLH5
PDF下载: 下载PDF文件 查看货源
内容描述: K20次家庭 [K20 Sub-Family]
分类和应用:
文件页数/大小: 62 页 / 1753 K
品牌: FREESCALE [ Freescale ]
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Peripheral operating requirements and behaviors  
TCLK  
TRST  
J14  
J13  
Figure 7. TRST timing  
6.2 System modules  
There are no specifications necessary for the device's system modules.  
6.3 Clock modules  
6.3.1 MCG specifications  
Table 13. MCG specifications  
Symbol Description  
Min.  
Typ.  
Max.  
Unit  
Notes  
fints_ft Internal reference frequency (slow clock) —  
32.768  
kHz  
factory trimmed at nominal VDD and 25 °C  
fints_t  
Internal reference frequency (slow clock) — user  
trimmed  
31.25  
39.0625  
0.6  
kHz  
Δfdco_res_t Resolution of trimmed average DCO output  
frequency at fixed voltage and temperature —  
using SCTRIM and SCFTRIM  
0.3  
%fdco  
1
Δfdco_t  
Total deviation of trimmed average DCO output  
frequency over voltage and temperature  
+0.5/-0.7  
0.3  
3
%fdco  
%fdco  
1
1
Δfdco_t  
Total deviation of trimmed average DCO output  
frequency over fixed voltage and temperature  
range of 0–70°C  
fintf_ft  
Internal reference frequency (fast clock) —  
factory trimmed at nominal VDD and 25°C  
3
4
5
MHz  
MHz  
kHz  
kHz  
fintf_t  
Internal reference frequency (fast clock) — user  
trimmed at nominal VDD and 25 °C  
floc_low  
Loss of external clock minimum frequency —  
RANGE = 00  
(3/5) x  
fints_t  
floc_high  
Loss of external clock minimum frequency —  
RANGE = 01, 10, or 11  
(16/5) x  
fints_t  
FLL  
Table continues on the next page...  
K20 Sub-Family Data Sheet, Rev. 4 5/2012.  
Freescale Semiconductor, Inc.  
25  
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