Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
ffll_ref FLL reference frequency range
fdco
Min.
Typ.
Max.
Unit
Notes
31.25
—
39.0625
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20
40
60
80
—
—
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
25
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
• fvco = 48 MHz
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
26
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
