General
Table 9. Device clock specifications (continued)
Symbol
fFLASH
fERCLK
Description
Min.
Max.
Unit
Notes
Flash clock
—
1
MHz
External reference clock
LPTMR clock
—
—
—
—
—
16
25
MHz
MHz
MHz
MHz
MHz
fLPTMR_pin
fLPTMR_ERCLK LPTMR external reference clock
16
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
50
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
13
7
ns
ns
• Slew enabled
—
—
ns
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
36
24
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
20
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
