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MK20DX64VLH5 参数 Datasheet PDF下载

MK20DX64VLH5图片预览
型号: MK20DX64VLH5
PDF下载: 下载PDF文件 查看货源
内容描述: K20次家庭 [K20 Sub-Family]
分类和应用:
文件页数/大小: 62 页 / 1753 K
品牌: FREESCALE [ Freescale ]
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General  
Table 6. Power consumption operating behaviors (continued)  
Symbol Description  
Min.  
Typ.  
Max.  
Unit  
Notes  
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V  
with POR detect circuit disabled  
0.176  
2.2  
0.859  
13.1  
23.9  
μA  
μA  
μA  
• @ –40 to 25°C  
• @ 70°C  
13  
• @ 105°C  
IDD_VBAT Average current with RTC and 32kHz disabled at  
3.0 V  
• @ –40 to 25°C  
• @ 70°C  
0.19  
0.49  
2.2  
0.22  
0.64  
3.2  
μA  
μA  
μA  
• @ 105°C  
IDD_VBAT Average current when CPU is not accessing  
RTC registers  
9
• @ 1.8V  
• @ –40 to 25°C  
• @ 70°C  
0.57  
0.90  
2.4  
0.67  
1.2  
μA  
μA  
μA  
• @ 105°C  
• @ 3.0V  
3.5  
• @ –40 to 25°C  
• @ 70°C  
0.67  
1.0  
0.94  
1.4  
μA  
μA  
μA  
• @ 105°C  
2.7  
3.9  
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See  
each module's specification for its supply current.  
2. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral  
clocks disabled.  
3. 50MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral  
clocks enabled, and peripherals are in active operation.  
4. Max values are measured with CPU executing DSP instructions  
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.  
6. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.  
Code executing from flash.  
7. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled  
but peripherals are not in active operation. Code executing from flash.  
8. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.  
9. Includes 32kHz oscillator current and RTC operation.  
5.2.5.1 Diagram: Typical IDD_RUN operating behavior  
The following data was measured under these conditions:  
• MCG in FBE mode  
• USB regulator disabled  
• No GPIOs toggled  
K20 Sub-Family Data Sheet, Rev. 4 5/2012.  
16  
Freescale Semiconductor, Inc.  
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