Nonswitching electrical specifications
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 9. EGPIO General Control Timing
Symbol
G1
Description
Min.
Max.
Unit
Bus clock from CLK_OUT pin high to GPIO output valid
—
1
32
—
ns
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
G3
G4
GPIO input valid to bus clock high
28
—
—
4
ns
ns
Bus clock from CLK_OUT pin high to GPIO input invalid
GPIO pin interrupt pulse width (digital glitch filter disabled)
Synchronous path1
1.5
—
Bus
clock
cycles
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled)
100
50
—
—
ns
ns
ns
Asynchronous path2
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
Asynchronous path2
External reset pulse width (digital glitch filter disabled)
Mode select (MS) hold time after reset deassertion
100
2
—
—
Bus
clock
cycles
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Bus clock
G1
G2
Data outputs
G3
G4
Data inputs
Figure 3. EGPIO timing diagram
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
19
FREESCALE [ Freescale ]
