Nonswitching electrical specifications
5. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
6. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks enabled, but
peripherals are not in active operation. Code executing from flash memory.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
8. OSC clocks disabled.
9. All pads disabled.
10. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
11. RTC function current includes LPTMR with OSC enabled with 32.768 kHz crystal at 3.0 V
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode, except for 50 MHz core (FEI mode)
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
• For the ALLON curve, all peripheral clocks are enabled, but peripherals are not in
active operation
• USB Voltage Regulator disabled
• No GPIOs toggled
• Code execution from flash memory with cache enabled
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
Freescale Semiconductor, Inc.
15
FREESCALE [ Freescale ]
