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MCF51JU128VLH 参数 Datasheet PDF下载

MCF51JU128VLH图片预览
型号: MCF51JU128VLH
PDF下载: 下载PDF文件 查看货源
内容描述: [MCF51JU128]
分类和应用:
文件页数/大小: 73 页 / 1089 K
品牌: FREESCALE [ Freescale ]
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Peripheral operating requirements and behaviors  
5.4.2 Thermal attributes  
Board type Symbol  
Description  
64 LQFP 48 LQFP  
44  
32 QFN Unit Notes  
Laminate  
QFN  
Single-layer RθJA  
(1s)  
Thermal resistance, junction to  
ambient (natural convection)  
73  
54  
61  
48  
37  
79  
55  
66  
48  
34  
108  
98  
33  
81  
28  
13  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
1
1
1
1
2
Four-layer  
(2s2p)  
RθJA  
Thermal resistance, junction to  
ambient (natural convection)  
69  
Single-layer RθJMA  
(1s)  
Thermal resistance, junction to  
ambient (200 ft./min. air speed)  
91  
Four-layer  
(2s2p)  
RθJMA  
Thermal resistance, junction to  
ambient (200 ft./min. air speed)  
63  
RθJB  
Thermal resistance, junction to  
board  
44  
RθJC  
Thermal resistance, junction to case 20  
20  
31  
2.2  
6.0  
°C/W  
°C/W  
3
4
ΨJT  
Thermal characterization  
5.0  
4.0  
6.0  
parameter, junction to package top  
outside center (natural convection)  
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions  
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method  
Environmental Conditions—Forced Convection (Moving Air).  
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions  
—Junction-to-Board.  
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate  
temperature used for the case temperature. The value includes the thermal resistance of the interface material between  
the top of the package and the cold plate.  
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions  
—Natural Convection (Still Air).  
6 Peripheral operating requirements and behaviors  
6.1 Core modules  
6.1.1 Debug specifications  
Table 12. Background debug mode (BDM) timing  
Number  
Symbol  
tMSSU  
Description  
Min.  
500  
Max.  
Unit  
1
2
BKGD/MS setup time after issuing background  
debug force reset to enter user mode or BDM  
ns  
µs  
tMSH  
BKGD/MS hold time after issuing background  
debug force reset to enter user mode or BDM1  
100  
MCF51JU128 Data Sheet, Rev. 4, 01/2012.  
Freescale Semiconductor, Inc.  
21  
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