Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from RAM, exercising
flash memory
3
—
—
20
20
23.5
25
mA
mA
• @ 1.8 V
• @ 3.0 V
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
5.8
6.8
mA
4
IDD_STOP
Stop mode current at 3.0 V
• @ –40 to 25 °C
—
—
—
0.34
0.90
0.63
0.41
1.8
mA
mA
mA
• @ 105 °C
IDD_VLPR
Very low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.32
5
6
IDD_VLPR
Very low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
0.78
0.15
1.46
0.62
mA
IDD_VLPW
IDD_VLPS
Very low-power wait mode current at 3.0 V
mA
μA
7
8
Very low-power stop mode current at 3.0 V
• @ –40 to 25 °C
—
—
19
45
• @ 105 °C
145
312
IDD_LLS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_RTC
Low leakage stop mode current at 3.0 V
• @ –40 to 25 °C
8,9,10
8,9,10
8,9
—
—
3.0
4.8
μA
μA
• @ 105 °C
53.3
157
Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25 °C
—
—
1.8
3.3
μA
μA
• @ 105 °C
39.2
115
Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25 °C
—
—
1.6
2.8
65
μA
μA
• @ 105 °C
22.2
Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25 °C
8,9
—
—
1.4
2.6
50
μA
μA
• @ 105 °C
17.6
Average current adder for real-time clock
function
11
—
0.7
—
μA
• @ –40 to 25 °C
1. The analog supply current is the sum of the active current for each of the analog modules on the device. See each
module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
14
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
