(1)
Table 1-8. Pin-Out Summary
Internal Pull
Resistor
Package Pin
Function
Power
Description
Supply
QFP
80
LQFP
64
QFN
48
2nd
Func.
3rd
Func.
Reset
State
Pin
CTRL
71
72
73
74
75
76
77
78
79
56
57
58
59
60
61
62
63
64
42
43
44
45
46
47
48
-
PM4
PM3
MOSI
SS
—
—
—
VDDX
VDDX
VDDX
VDDX
VDDX
—
PERM/PPSM Disabled Port M I/O, MOSI of SPI
PERM/PPSM Disabled Port M I/O, SCK of SPI
PERM/PPSM Disabled Port M I/O, SS of SPI0
PERM/PPSM Disabled Port M I/O, TX of CAN
PERM/PPSM Disabled Port M I/O, RX of CAN
PM2
MISO
TXCAN
RXCAN
—
PM1
PM0
VSSX1
VDDX1
PP7
—
—
—
—
—
—
—
—
—
—
KWP7
KWP5
VDDX
VDDX
PERP/PPSP
PERP/PPSP
Disabled Port P I/O, interrupt
-
PP5
PWM5
PWM4
Disabled Port P I/O, interrupt,
PWM channel
80
-
-
PP4
KWP4
VDDX
PERP/PPSP
Disabled Port P I/O, interrupt,
PWM channel
1. Table shows a superset of pin functions. Not all functions are available on all derivatives
2. VRH and VDDA share single pin on 48 pin package option
3. VRL and VSSA share single pin on 64 and 48 pin package option
NOTE
For devices assembled in 48-pin and 64-pin packages all non-bonded out pins should be configured as
outputs after reset in order to avoid current drawn from floating inputs. Refer to Table 1-8 for affected
pins.
FREESCALE [ Freescale ]
