Pulse-Width Modulator (PWM8B6CV1) Block Description
Table 10-12 is used to summarize which channels are used to set the various control bits when in 16-bit
mode.
Table 10-12. 16-bit Concatenation Mode Summary
CONxx
PWMEx
PPOLx
PCLKx
CAEx
PWMx Output
CON45
CON23
CON01
PWME5
PWME3
PWME1
PPOL5
PPOL3
PPOL1
PCLK5
PCLK3
PCLK1
CAE5
CAE3
CAE1
PWM5
PWM3
PWM1
10.4.2.8 PWM Boundary Cases
Table 10-13 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
or center aligned) and 8-bit (normal) or 16-bit (concatenation):
Table 10-13. PWM Boundary Cases
PWMDTYx
PWMPERx
PPOLx
PWMx Output
0x0000
>0x0000
1
Always Low
(indicates no duty)
0x0000
(indicates no duty)
>0x0000
0
1
0
1
0
Always High
Always High
Always Low
Always High
Always Low
XX
0x0000(1)
(indicates no period)
0x00001
(indicates no period)
XX
>= PWMPERx
>= PWMPERx
XX
XX
1. Counter = 0x0000 and does not count.
10.5 Resets
The reset state of each individual bit is listed within the register description section (see Section 10.3,
“Memory Map and Register Definition,” which details the registers and their bit-fields. All special
functions or modes which are initialized during or just following reset are described within this section.
•
•
The 8-bit up/down counter is configured as an up counter out of reset.
All the channels are disabled and all the counters don’t count.
10.6 Interrupts
The PWM8B6CV1 module has only one interrupt which is generated at the time of emergency shutdown,
if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag
PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA=1 or when
PWMENA is being asserted while the level at PWM5 is active.
A description of the registers involved and affected due to this interrupt is explained in Section 10.3.2.15,
“PWM Shutdown Register (PWMSDN).”
S12P-Family Reference Manual, Rev. 1.13
362
Freescale Semiconductor
FREESCALE [ Freescale ]
