欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
 浏览型号MC9S12P64CFT的Datasheet PDF文件第355页浏览型号MC9S12P64CFT的Datasheet PDF文件第356页浏览型号MC9S12P64CFT的Datasheet PDF文件第357页浏览型号MC9S12P64CFT的Datasheet PDF文件第358页浏览型号MC9S12P64CFT的Datasheet PDF文件第360页浏览型号MC9S12P64CFT的Datasheet PDF文件第361页浏览型号MC9S12P64CFT的Datasheet PDF文件第362页浏览型号MC9S12P64CFT的Datasheet PDF文件第363页  
Pulse-Width Modulator (PWM8B6CV1) Block Description  
E = 100 ns  
DUTY CYCLE = 75%  
PERIOD = 400 ns  
Figure 10-37. PWM Left Aligned Output Example Waveform  
10.4.2.6 Center Aligned Outputs  
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the  
corresponding PWM output will be center aligned.  
The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is  
equal to 0x0000. The counter compares to two registers, a duty register and a period register as shown in  
the block diagram in Figure 10-35. When the PWM counter matches the duty register the output flip-flop  
changes state causing the PWM waveform to also change state. A match between the PWM counter and  
the period register changes the counter direction from an up-count to a down-count. When the PWM  
counter decrements and matches the duty register again, the output flip-flop changes state causing the  
PWM output to also change state. When the PWM counter decrements and reaches 0, the counter direction  
changes from a down-count back to an up-count and a load from the double buffer period and duty  
registers to the associated registers is performed as described in Section 10.4.2.3, “PWM Period and  
Duty.” The counter counts from 0 up to the value in the period register and then back down to 0. Thus the  
effective period is PWMPERx*2.  
NOTE  
Changing the PWM output mode from left aligned output to center aligned  
output (or vice versa) while channels are operating can cause irregularities  
in the PWM output. It is recommended to program the output mode before  
enabling the PWM channel.  
PPOLx = 0  
PPOLx = 1  
PWMDTYx  
PWMPERx  
PWMDTYx  
PWMPERx  
Period = PWMPERx*2  
Figure 10-38. PWM Center Aligned Output Waveform  
To calculate the output frequency in center aligned output mode for a particular channel, take the selected  
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period  
register for that channel.  
PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx)  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
359  
 复制成功!